1. Field of the Invention
The invention relates to a wiring board and a method of manufacturing the same, and, more particularly, to a wiring board suitable for mounting, for example, an area array type semiconductor element by flip-chip connection, and a method of manufacturing the same.
2. Description of Related Art
As a semiconductor integrated circuit element that is a semiconductor element, there has heretofore been a so-called area array type semiconductor integrated circuit element in which a large number of electrode terminals are arranged in a lattice form substantially the entire one main surface thereof.
As a method of mounting the above semiconductor integrated circuit element onto a wiring board, flip chip connection is employed. In the flip chip connection, firstly, the upper surface of a semiconductor element connection pad disposed on the wiring board is exposed correspondingly to the arrangement of the electrode terminals of the semiconductor integrated circuit element. Subsequently, the exposed upper surfaces of the semiconductor element connection pads and the electrode terminals of an semiconductor integrated circuit element are opposed to each other, and the electrical connection therebetween is made through conductive bumps composed of solder, metal, or the like.
Recently, there have been attempts to increase the mounting density of semiconductor elements or electronic components onto a wiring board by flip-chip connection, and further mounting a different electronic component by a solder ball connection or a wire bond connection (for example, refer to patent document 1).
FIG. 30 is a schematic sectional view showing an example of conventional wiring boards in which an area array type semiconductor integrated circuit element as a semiconductor element is mounted by flip-chip connection, and a semiconductor element mounting substrate as another electronic component is mounted thereon by solder ball connection. FIG. 31 is a plan view showing the wiring board shown in FIG. 30.
As shown in FIG. 30, the conventional wiring board 110 has an insulation substrate 101. The insulation substrate 101 is constituted by laminating a plurality of build-up insulation layers 101b on the upper and lower surfaces of a core insulation substrate 101a. A core wiring conductor 102a and a build-up wiring conductor 102b are deposited onto the interior and the surface of the insulation substrate 101. A protective solder resist layer 103 is deposited onto the uppermost surface of the insulation substrate 101. A semiconductor element mounting portion 101A for mounting a semiconductor integrated circuit element E1 is formed on an upper surface mid part of the insulation substrate 101. An electronic component mounting portion 101B for mounting a semiconductor element mounting substrate E2 is formed on an upper surface outer peripheral part of the insulation substrate 101.
A plurality of through-holes 104 extend between the upper surface and the lower surface of the core insulation substrate 101a. The core wiring conductor 102a is deposited onto the upper and lower surfaces of the insulation substrate 101a and the inner surfaces of these through-holes 104. A plugged resin 105 fills the interior of these through-holes 104. A plurality of via holes 106 are formed in the plurality of build-up insulation layers 101b, respectively. The build-up wiring conductor 102b is formed by deposition on the surfaces of the individual insulation layers 101b and the inner surfaces of these via holes 106.
A part of the wiring conductor 102b which is deposited onto the outermost insulation layer 101b on the upper surface side of the wiring board 110 forms a semiconductor element connection pad 102A. The semiconductor element connection pad 102A is a circular pad electrically connected by flip-chip connection through a conductive bump B1 to an electrode terminal of the semiconductor integrated circuit element E1 in the semiconductor element mounting portion 101A. As shown in FIG. 31, a plurality of the semiconductor element connection pads 102A are arranged in a lattice form.
A part of the wiring conductor 102b which is deposited onto the outermost insulation layer 101b on the upper surface side of the wiring board 110 forms a electronic component connection pad 102B. The electronic component connection pad 102B is a circular pad electrically connected by solder ball connection through a solder ball B2 to an electrode terminal of the semiconductor element mounting substrate E2 as an electronic component in the electronic component mounting portion 101B. A plurality of the electronic component connection pads 102B are disposed side by side.
Outer peripheral parts 102A2 and 102B2 of the semiconductor element connection pads 102A and the electronic component, connection pads 102B are covered with a solder resist layer 103, and the mid parts of the upper surfaces thereof are exposed from the solder resist layer 103. The electrode terminals of the semiconductor integrated circuit element E1 are electrically connected to exposed parts 102A1 of the semiconductor element connection pad 102A through the conductive bumps 81 composed of solder, metal, or the like. The electrode terminals of the semiconductor element mounting substrate E2 are electrically connected through the solder balls B2 to the exposed parts 102B1 of the electronic component connection pads 102B.
On the other hand, a part of the wiring conductor 102b which is deposited onto the outermost insulation layer 101b on the lower surface side of the wiring board 110 forms an external connection pad 102C. The external connection pad 102C is a circular pad electrically connected to a wiring conductor of an external electric circuit substrate. A plurality of the external connection pads 102C are arranged in a lattice form. The outer peripheral parts of these external connection pads 102C are covered with the solder resist layer 103. The upper surface mid parts of these external connection pads 102C are exposed from the solder resist layer 103. The wiring conductor of the external electric circuit substrate is electrically connected through a solder ball B3 to the exposed parts of the external connection pads 102C.
The solder resist layer 103 protects the outermost wiring conductor 102b, and defines the exposed parts of the semiconductor element connection pads 102A, the electronic component connection pads 102B and the external connection pads 102C, respectively. The solder resist layer 103 is formed as follows. Firstly, a thermosetting resin paste or a film having photosensitivity is laminated on the outermost insulation layer 101b where the wiring conductor 102b is formed. Subsequently, exposure and development are performed to cover the outer peripheral parts of the semiconductor element connection pads 102A and the electronic component connection pads 102B and the external connection pads 102C, and also have openings for exposing their respective mid parts, followed by curing.
Consequently, the exposed parts 102A1 and 102B1 of the semiconductor element connection pads 102A and the electronic component connection pads 102B are recessed from the surface of the solder resist layer 103. Further, the outer peripheral parts 102A2 and 102B2 of the semiconductor element connection pads 102A and the electronic component connection pads 102B are buried under the solder resist layer 103 with a predetermined width.
After the electrode terminals of the semiconductor integrated circuit element E1 and the semiconductor element connection pads 102A are electrically connected to each other through the conductive bumps B1, a filling resin U1 called underfill composed of a thermosetting resin, such as epoxy resin, is filled into the space between the semiconductor integrated circuit element E1 and the wiring board 110, thereby mounting the semiconductor integrated circuit element E1 onto the wiring board 110. Further thereon, the electrode terminals of the semiconductor element mounting substrate E2 and the electronic component connection pads 102B are electrically connected to each other through the solder balls B2, thereby mounting the semiconductor element mounting substrate E2 onto the wiring board 110. This achieves high-density mounting of semiconductor elements and the electronic components onto the wiring board 110.
Recently, the high integration of the semiconductor integrated circuit element E1 has been advanced rapidly, and the arrangement pitch of the electrode terminals on the semiconductor integrated circuit element E1 becomes narrower (for example, less than 150 μm). Accordingly, the arrangement pitch of the semiconductor element connection pads 102A, to which the electrode terminals of the semiconductor integrated circuit element E1 are connected by flip-chip connection, also becomes narrower (for example, less than 150 μm).
For achieving the narrow pitch of the semiconductor element connection pads 102A, it is unavoidable to decrease at least one of the diameter of the semiconductor element connection pads 102A and the distance between the adjacent semiconductor element connection pads 102A and 102A. When the diameter of the semiconductor element connection pads 102A is decreased, the diameter of the exposed parts 102A1 from the solder resist layer 103 in the semiconductor element connection pad 102A is correspondingly decreased. When the diameter of the exposed parts 102A1 is small, the development during the formation of the solder resist layer 103 becomes insufficient, and the resin residue of the solder resist layer 103 becomes liable to remain at the exposed parts 102A1. Additionally, the connection area between the semiconductor integrated circuit element E1 and the conductor bump B1 becomes small, making it difficult to firmly and satisfactorily connect the electrode terminals of the semiconductor integrated circuit element E1 and the semiconductor element connection pads 102A through the conductor bumps B1.
For achieving satisfactory connection between the semiconductor integrated circuit element E1 and the semiconductor element connection pads 102A, without leaving the resin residue of the solder resist layer 103 on the exposed part 102A1 of the semiconductor element connection pads 102A, it is desirable to set the diameter of each of the exposed parts 102A1 to not less than 70 μm.
It is usually necessary that the width of the solder resist layer 103 covering the outer peripheral parts 102A2 of the semiconductor element connection pads 102A be not less than 15 μm in terms of positioning accuracy between the semiconductor element connection pads 102A and solder resist layer 103. Therefore, when it is ensured that the diameter of the exposed part 102A1 is approximately 70 μm, the diameter of the semiconductor element connection pads 102A is approximately 100 μm.
For example, in the case where the arrangement pitch of the semiconductor element connection pad 102A is 140 μm, if the diameter of the semiconductor element connection pads 102A is 100 μm, the distance between the adjacent semiconductor element connection pads 102A and 102A is 40 μm. If the distance between the adjacent semiconductor element connection pads 102A and 102A is 40 μm, it becomes difficult to form, for example, a strip-shaped wiring conductor having a width of approximately 15 μm within this distance, while ensuring a sufficient distance of approximately 15 μm between the opposite semiconductor element connection pads 102A.
The following problem may arise when the strip-shaped wiring conductor cannot be formed between the adjacent semiconductor element connection pads 102A and 102A. That is, the strip-shaped wiring conductor extending outside of the mounting portion 101A cannot be disposed from the plurality of semiconductor element connection pads 102A arranged in the lattice form, except for the semiconductor element connection pads 102A lying on the outermost periphery, and hence the degree of freedom in the design of the wiring board 110 is lowered.
Patent document 1: Japanese Unexamined Patent Application Publication No. 2000-244088